1. Technical Field
The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device for preventing a program disturbance and a method of programming the nonvolatile memory device.
2. Discussion of the Related Art
Flash memory devices are useful as auxiliary memory devices for portable devices because of their long data retention, low power consumption, and high impact durability. Flash memory devices may store data in a series of cells as electronic charges within a potential barrier. Programming of a memory cell may include injection of electrons into a potential barrier or tunneling of elections into the potential barrier. Erasure of the memory cell may be implemented by electron tunneling.
In particular, NAND flash memory devices in which a predetermined number of memory cells are connected in series are more useful as auxiliary memory devices for high capacity portable devices because of their smaller cell size and higher degree of integration than NOR flash memory devices in which memory cells are connected in parallel.
In NAND flash memory, memory cells may be organized in strings, pages, and blocks. A string is made up of plurality of memory cells serially connected to one bit line. A page consists of a group of memory cells connected to one word line. Each block of memory cells includes a plurality of pages. In such NAND flash memory devices configured as described above, reading and programming are performed on a page basis. Accordingly, no less than one full page of memory cells may be read or programmed. Erasure of the memory cells is performed on a block basis and thus no less than one full block of memory cells may be erased.
FIG. 1 is a circuit diagram illustrating a voltage applied during a program operation of a conventional NAND flash memory device. Referring to FIG. 1, a memory cell array 100 includes first and second memory strings A0 and A1 in which memory cells are connected to common word lines WL0 through WLn. The first memory string A0 is connected to a first bit line BL0, and the second memory string A1 is connected to a second bit line BL1. In the first memory string A0, memory cell transistors MT0A through MTnA have floating gates and are serially connected. A drain of the memory cell transistor MT0A is connected to the first bit line BL0 through a string selection transistor SG1A connected to a string selection line SSL. A source of the memory cell transistor MTiA is connected to a ground voltage VSS through a ground selection transistor SG2A connected to a ground selection line GSL. In the second memory string A1, memory cell transistors MT0B through MTnB have floating gates and are serially connected. A drain of the memory cell transistor MT0B is connected to the second bit line BL1 through a string selection transistor SG1B. A source of the memory cell transistor MTnB is connected to a ground voltage VSS through a ground selection transistor SG2B.
A program operation of a flash memory that occurs after an erase operation is performed as follows. It may be assumed that the memory cell transistor MTiA of the first memory string A0 is the flash memory cell to be programmed. A voltage of 0 V is applied to the first bit line BL0 and the string selection transistor SG1A is turned on, the first memory string A0 is connected to the first bit line BL0 and the string selection transistor SG2A is turned off A program voltage Vpgm of, for example, 14 to 20 V, is applied to the selected word line WLi, and a pass voltage Vpass of, for example, 7 to 10 V, is applied to the non-selected word lines WL0 through WLn. Accordingly, electrons of the memory cell transistor MTiA are tunneled from a channel to the floating gate, thereby shifting a threshold voltage of the memory cell transistor MTiA to a positive voltage.
Since the program operation is performed on a page basis, if the program voltage Vpgm is applied to the word line WLi, the same program voltage Vpgm is also applied to the gate of the memory cell transistor MTiB that is part of the second memory string A1 even though the second memory string A1 has not been selected. Accordingly, in one page, the memory cell transistor MTiA which is to be programmed and the memory cell transistor MTiB (referred to as program inhibit cell) which is not to be programmed are connected to one word line WLi, and thus the program voltage Vpgm is applied to all cells that are connected to the selected word line WLi. As a result, the program inhibit cell of the memory cell transistor MTiB may be soft programmed due to the program voltage Vpgm, thereby causing a program disturbance.
In order to prevent the program disturbance of the program inhibit cell of the memory cell transistor MTiB, attempts have been made to reduce the program voltage Vpgm applied to the selected word line WLi or to increase a channel voltage. Since the attempt to reduce the program voltage Vpgm is greatly dependent on the characteristics of the program inhibit cell of the memory cell transistor MTiB, it may not be practical to reduce the program voltage Vpgm applied to the selected word lime WLi. The channel voltage may, however, be increased by applying a power voltage VDD to the second bit line BL1 using self-boosting by a capacitive coupling between the gate and the channel.
Alternatively, the channel voltage may be increased due to the self-boosting by the capacitive coupling between the gate and the channel by increasing the magnitude of change in a voltage applied to the selected word line WLi. Accordingly, there is a demand for a method of increasing the magnitude of change in the voltage applied to the selected word line WLi.